Projects


CHREC 2008 Projects (F=Florida, G=GWU, B=BYU, V=VT)
  F1-08: System-Level Formulation for Algorithm/Architecture Exploration
  F2-08: Application Performance Analysis
  F3-08: Case Studies in Multi-FPGA Application Design
  F4-08: Reconfigurable Fault Tolerance and Partial Reconfiguration
  F5-08: Device Characterization & Design Space Exploration
  G5-08: Library Portability for HLL Acceleration Cores
  G6-08: Intelligent Deployment of IP Cores
  G7-08: Partial Run-Time Reconfiguration for HPRC
  B1-08: Core Library Framework for HPC/HPEC
  B2-08: Heterogeneous Architectures for HPEC RC
  B3-08: High-Reliability RC Design Tools and Techniques
  B4-08: Reliable RC DSP/Comm Systems
  V1-08: Model-Based Engineering Framework for HPRC Applications
  V2-08: Process-to-Core Mapping for Advanced Architectures

ONE-PAGE PROJECT SUMMARIES: Florida, GWU, BYU, VT

CHREC 2007 Projects (F=Florida, G=GWU)
  F1-07: Simulative Performance Prediction
  F2-07: Performance Analysis & Profiling
  F3-07: Application Case Studies
  F4-07: Partial RTR Architecture for Qualified HPEC Systems
  F5-07: FPLD Device Architectures and Tradeoffs
  G1-07: Profiling Applications for HW/SW Partitioning and Co-scheduling
  G4-07: High-Level Languages Productivity - an HPC Perspective
  G5-07: Library Portability and Acceleration Cores

© 2008, NSF CHREC Center.  All Rights Reserved.